This application mclaims priority of German patent application 199 29 419.4 filed Jun. 26, 1999.
1. Field of the Invention
The invention relates to a synchronous communication bus for the transfer of data between circuit modules, which are connected to the communication bus. The communication bus is a register control bus comprising an address bus, a data bus and a control bus. The circuit modules either request data or, signal readiness to send an interrupt signal. Each circuit module comprises a synchronous register interface.
2. Description of the Related Art
Bus architectures for communication between circuit modules are especially adequately known from micro-computers. A typical system bus for a micro-computer is described in Scholze, Rainer: xe2x80x9cEinfxc3x85hrung in die Mikrocomputer-Technik: Grundlagen, Programmierung, Schaltungstechnikxe2x80x9d [Introduction to micro-computer technology: principles, programming, circuit technology], Teubner-Studienskripten [Teubner study texts], Teubner-Verlag, Stuttgart, 1985, pages 34 through 37. A system bus comprises a data bus, an address bus and a control bus that are connected to and controlled by a micro-processor. Additional circuit modules, such as e.g. main memories, input/output channels, etc., are connected to the bus. Data from or, respectively, to the micro-processor are transferred bi-directionally via the data bus. The micro-processor transfers the current address to a circuit module, e.g. a memory address, the address of an input/output channel or address of of a supplementary component, via the address bus. The addresses are thereby cascaded so that part of the digital address can be used for the selection of the circuit module. Control signals, e.g. writing and reading signals, etc., are transferred to the control bus in order to trigger the circuit modules. The bus system is controlled by the micro-processor provided for establishing the addresses and control signals and for triggering the passive circuit modules connected to the bus.
In addition, multi-micro-processor systems are known in which several active micro-processors or, respectively, circuit modules have access to the system bus. A central bus allocation logic unit is thereby provided that controls the access to the system bus since only one circuit module can have access to the system bus at any one time. The bus allocation logic unit is also known as an interrupt-controller. The circuit modules send interrupt signals in order to request access to the system bus. The interrupt signals are controlled in terms of their priority and, depending on the priority of the interrupt signal, the circuit module in question receives information via the system bus in question for the duration of an exchange of data.
In Meiling, Fxc3x85lle: xe2x80x9cMikroprozessoren und Mikrorechnerxe2x80x9d [Micro-processors and micro-calculators], Akademie-Verlag, Berlin, 1988, pages 193 through 197, a communication bus is described that comprises a control bus, an address bus and a data bus in which the circuit modules each comprise a data buffer in the form of an intermediate memory and a programmable control register for communication with a central micro-processor. The circuit modules are provided for sending the interrupt signals to the central micro-processor that synchronizes the communication bus and controls the input/output operations of the circuit modules.
So-called DMA control elements are known for transferring large blocks of data from one circuit module to a memory element, in which a DMA controller is assisting bus control of the control elements without in-line hook up of the micro-processor. The DMA control element is described in Rainer Scholze, xe2x80x9cEinfxc3x85hrung in die Mikrocomputertechnik-Grundlagen, Programmierung, Schaltungstechnikxe2x80x9d [Introduction to micro-computer technology-principles, programming, circuit technology], Teubner-Verlag, Stuttgart, 1985, pages 274 through 277. A DMA controller serves merely for controlling the communication of circuit modules with one single established memory component. A higher control of the communication bus takes place in addition to the DNA control of the circuit modules.
The problem presents itself during the development and programming of integrated circuits, which have been assembled in a modular fashion, of hooking up the modules in line with a bus system, which is as universal as is possible, in such a way that the bus is used to its full capacity as well and permits a high rate of data transmission via the bus. The control of the circuit modules has to be as simple as possible in this regard so that the communication bus is capable of being modified via simple programming. In addition, the circuit modules have to be capable of being synchronized without great expense.
In accordance with the invention, an additional data bus and additional control bus are provided beyond the conventional asynchronous processor bus systems comprising an address bus, a data bus and a control bus. A bus control unit synchronizes the control bus with an additional data bus, and the bus control unit has register interfaces which are triggered by clearing signals from the additional control bus. The conventional asynchronous processor bus system is merely used for controlling the circuit modules but not for controlling the transfer of data between the control modules.
A command memory can be provided in the bus control unit, whereby a table of command sequences is filed in the command memory. In this case, one command sequence can then be defined for each interrupt, whereby the command sequences comprise at least the memories that are to be selected, the number of data that are to be transferred and data for selection of a reading and writing mode. Thus the bus access by the bus control unit can be controlled automatically as a function of the interrupt. Reading out of data from defined circuit modules and writing of the data into other defined circuit modules, and/or the microprocessor is controlled by the command sequences. As a result, the bus can be adapted in a simple manner, via software, to the specific circuit requirements in question after the circuit modules have been hooked up in-line to the standard bus to give the desired circuit. A priority can thereby be established for every interrupt so that the implementation of the interrupt and/or the associated command sequences can take place in the sequential order of interrupt priorities. This has the advantage that the bus control unit can easily be modified subsequently by changing the priorities but without having to change the command sequences. This can be necessary, for example, when, during test operation, it is found that a memory is overflowing or, respectively, emptying out.
In accordance with the invention, the communication bus is synchronized via signals for clearing the memories by way of the feature that the clearing signals serve for supplying the communication bus with timing pulses. In addition, it is advantageous if the additional data bus has a reading data bus for reading data from a circuit module and a writing data bus for writing data into a circuit module. Data can then be written directly from one circuit module into another circuit module with the help of a pipeline procedure without further losses of timing pulses with the exception of the first and the last timing pulse. For this purpose, the invention provides an intermediate memory between the reading data bus and the writing data bus so that, in a first step, an item of data is first written into the intermediate memory via the reading data bus and, in a second step, it is written from the intermediate memory, via the writing data bus, into at least one other circuit module. The intermediate memory is advantageously a multiplexer. Multiplexing can be processed by means of a three state (tristate) bus.
A short command memory can be provided in the bus control unit and an interrupt line provided between the bus control unit and a micro-processor so that the micro-processor can write command sequences in the short command memory if an interrupt is sent to the micro-processor. As a result, command sequences, which are active on a short-term basis, can be established for the interrupts of the circuit modules. The bus control unit is also capable of being modified during operation in this way.
In addition, the micro-processor is connected to the circuit modules and is constructed in such a way that a degree of filling of the FIFO memories with data is established by the micro-processor, whereby an interrupt is sent on reaching the established degree of filling. As a result, the circuit modules can be controlled centrally via the micro-processor or, respectively, via a program that is implemented by the micro-processor by means of simple parametrization of the memories.
The synchronous communication bus offers good capacity utilization of the timing pulse cycles. As a result of the design of the communication bus, semiconductor circuits, which have been assembled in a modular fashion, can be developed and adapted with ease via conventional means.